Design guideline of an ultra-thin body SOI MOSFET for low-power and high-performance applications

Abstract

With the decrease in gate length scaling, the leakage current has become more and more significant. Ultra-thin body (UTB) silicon-on-insulator (SOI) metal–oxide semiconductor field effect transistors (MOSFETs) are promising candidates for sub-50 nm MOSFETs. In this paper, we investigate the trade-off of a 50 nm undoped-body UTB SOI device with different gate workfunctions (Φm) and silicon body thickness (TSi). For the first time, the optimal regions of gate workfunctions and the silicon body thickness for low operating power (LOP) and high-performance logic (HP) applications are given respectively, which shed light on UTB MOSFET design. The simulation results show that in comparison with HP devices, LOP devices can exhibit a relatively wider design window. It is identified that UTB SOI devices can offer a better device solution for LOP applications.