3D Network-on-Chip system communication using minimum number of TSVs

Abstract

Three-dimensional networks-on-chip (3D NoC) using through-silicon-via (TSV) can significantly improve the performance and the degree of integration of the system-on-chip. However, TSV accompanies some overheads such as area, cost, and capacitance, so it must be balanced between performance and cost. In this paper, an efficient 3D NoC design technique that minimizes the number of TSVs with a new vertical communication method is suggested. The proposed technique showed only 8.1% decrease in performance while area saving is 39.5% compared to the 3D NoC with 8 TSVs. It is expected to improve performance further as the number of layers increases.