2013 · 10 citations · 4 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignSystem-on-chip DesignData CompressionImage CompressionMemory Hierarchy OptimizationSource CodingBuffer SharingLossless Image CompressionLossless Video CompressionMemory BandwidthMemory Bandwidth OptimizationPower ConsumptionPower Consumption OptimizationVideo Compression
An architecture of H.265/HEVC video decoder for next generation video applications is presented. By exploiting near-lossless data compression and Sharing Above Line Buffer (SALB) schemes, both memory bandwidth and on-chip storage can be reduced. Moreover, cross-stage scheduling is applied to the 4-stage decoding pipeline to minimize idle computations. Fabricated in 90nm 1P9M CMOS process, the test chip of the proposed H.265/HEVC video decoder occupies an area of 1.60×1.98mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to achieve 1080p@30fps and 720p@30fps realtime decoding with power consumption of 36.90 and 9.57mW.
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A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications
Chao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar et al. · 2013 · 32 citations