A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses

TLDR

Implementing compact, low‑power artificial neural processing systems with real‑time on‑line learning abilities remains an open challenge. The paper presents a full‑custom mixed‑signal VLSI device with neuromorphic learning circuits that emulate real spiking neurons and dynamic synapses to explore computational neuroscience models and build brain‑inspired computing systems, and details the architecture and experimental results. The architecture supports on‑chip configuration of diverse network connectivities, including recurrent and deep networks, and incorporates 128 K analog synapses and 256 neuron circuits with biologically plausible dynamics and bi‑stable spike‑based plasticity, complemented by asynchronous digital logic for tuning synapse and neuron properties and network configurations. The prototype, fabricated in 180 nm CMOS, occupies 51.4 mm², consumes ~4 mW during typical attractor‑network experiments, and its support for cortical‑like modules with plasticity mechanisms enables intelligent autonomous systems with on‑line learning.

Abstract

Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm(2), and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.