Publication | Closed Access
Taming hardware event samples for FDO compilation
70
Citations
19
References
2010
Year
Unknown Venue
EngineeringMachine LearningHardware Verification LanguageHardware Event SamplesComputer ArchitectureSoftware EngineeringSoftware AnalysisFormal VerificationHardware SecurityData ScienceEdge ProfilesFeedback-directed OptimizationCompilersParallel ComputingApplication Runtime PerformancePerformance PredictionRuntime VerificationProfiling ToolComputer EngineeringComputer ScienceProgram OptimizationPerformance Analysis ToolHardware EmulationHardware AccelerationProgram AnalysisSoftware TestingParallel Programming
Feedback-directed optimization (FDO) is effective in improving application runtime performance, but has not been widely adopted due to the tedious dual-compilation model, the difficulties in generating representative training data sets, and the high runtime overhead of profile collection. The use of hardware-event sampling to generate estimated edge profiles overcomes these drawbacks. Yet, hardware event samples are typically not precise at the instruction or basic-block granularity. These inaccuracies lead to missed performance when compared to instrumentation-based [email protected] In this paper, we use multiple hardware event profiles and supervised learning techniques to generate heuristics for improved precision of basic-block-level sample profiles, and to further improve the smoothing algorithms used to construct edge profiles. We demonstrate that sampling-based FDO can achieve an average of 78% of the performance gains obtained using instrumentation-based exact edge profiles for SPEC2000 benchmarks, matching or beating instrumentation-based FDO in many cases. The overhead of collection is only 0.74% on average, while compiler based instrumentation incurs 6.8%-53.5% overhead (and 10x overhead on an industrial web search application), and dynamic instrumentation incurs 28.6%-1639.2% overhead.
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