Design options for hetero-junction tunnel FETs with high on current and steep sub-threshold voltage slope

Abstract

This work presents a systematic design study of nanowire Tunnel-FETs at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =17nm employing a 3D Poisson-NEGF solver based on a 8×8 k·p Hamiltonian and including phonon scattering. In particular: (a) we revisit the design of GaSb-InAs based hetero-junction tunnel-FETs showing that this system is unlikely to yield a broken bangap profile at the very narrow features necessary for a good sub-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> slope value; (b) we propose new design options for hetero-junction tunnel-FETs, relying on the use of strain and of a graded molar fraction (x <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> ) in Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xM</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(1-xM)</sub> Sb, which improve remarkably on current preserving optimal sub-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> slopes; (c) we show that interface defects can frustrate any design strategy aiming at sub-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> slope values below 60mV/dec.