2014 · 10 citations · 11 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDc-dc ConversionDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersCapacitorsCmos Analog Circuit DesignCmos Analog Integrated CircuitsComparator DesignDigital-to-analog Converters
A 0.3V 10-bit rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC) is realized in 0.18-μm CMOS process. While the supply is 0.3V, a double-boosted sampling switch and a supply-boosted time-domain comparator are proposed to decrease the on-resistance of the switches and improve the conversion time, respectively. To lower the power, differential dynamic switches are used to control the splitting capacitors of the digital-to-analog converter. This ADC achieves the SNDR of 54.57dB and the SFDR of 69.89dB, respectively. The power consumes 15.9nW at 5kS/s from a 0.3V supply. A figure-of-merit of 7.3fJ/conversion-step for this ADC is achieved.
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11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS
Hung-Yen Tai, Yao-Sheng Hu, Hung‐Wei Chen et al. · 2014 · 222 citations
Engineering, Computer Engineering, Electrical Engineering +17