All digital dividing ratio changeable type phase‐locked loop with a wide lock‐in range

Abstract

Abstract Today the All Digital Phase‐Locked Loop (ADPLL) is applied in many fields. However, previously proposed ADPLLs did not simultaneously implement a wide lock‐in range and a fast pull‐in. The proposed Dividing ratio Changeable ADPLL (DCPLL) is a method for automatically changing the dividing ratio of the counter in response to the frequency of the input signal and can obtain an extremely wide lock‐in range. The output jitter will always be three or fewer pulses of the fast reference clock. By performing remainder control of the dividing ratio during multiplication, an output signal that is a multiple of the constant pulse interval and has jitter characteristics equivalent to the basic operation can be obtained. Furthermore, the initial pull‐in is finished in one period of the input signal, which is the shortest time. Consequently, since a wide lock‐in range and a fast pull‐in can be simultaneously achieved, this DCPLL has many general‐purpose applications and is effective in the reference clock source in all types of portable devices and in bit synchronization in data communication. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 88(2): 41–49, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/ecja.20138