IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1993 · 75 citations · 34 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDesign OptimizationSystems ArchitectureControl-flow AnalysisData-flow AnalysisDesign SynthesisHigh-level SynthesisInterconnect ArchitectureMicroarchitecture DesignArchitectural SynthesisDataflow SynthesisFlow Graph ConstructionLower Bounds
The authors present a solution to the following problems related to architectural synthesis. (1) Given an input specification and a performance constraint, determine a lower bound number of resources (active and interconnect) required to execute the data flow graph while satisfying the performance constraint. (2) Determine a lower bound performance for executing an input specification for a given number of resources (active and interconnect). These bounds are close to the actual designs synthesized by several existing systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Bounds on Multiprocessing Timing Anomalies
Ron Graham · SIAM Journal on Applied Mathematics · 1969 · 2.4K citations