A 43.7mW 96GHz PLL in 65nm CMOS

Abstract

In this paper, a 96 GHz PLL, implemented in 65 nm CMOS, is presented that target W-band applications. PLL is composed of a VCO, a low-power divider chain with the division ratio of 256, a PFD, a charge pump (CP), and a 2nd-order loop filter (LF). In the VCO design, a symmetric inductor and a cross-coupled pair are adopted to achieve a high oscillation frequency and a low power consumption.For the divider chain, the four different divider topologies are adopted in a descendant order of the frequency.