A Minimally Invasive 64-Channel Wireless μECoG Implant

TLDR

Brain–machine interface systems need high‑resolution, chronic multisite cortical recordings, but current technologies are limited by high power, invasiveness, or lack of wireless transmission. This work presents a microsystem that overcomes these limitations by enabling chronic, wireless ECoG recording from the cortical surface. The system combines a flexible 64‑channel polymer electrode array and antenna with a 2.4 mm × 2.4 mm CMOS IC that digitizes signals at 1 kS/s with 1.2 µV noise, transmits data at 1 Mb/s via backscatter, and uses a dual‑mode rectifier to eliminate external decoupling components. Design optimizations achieve a 16× die‑area reduction, a 3× power‑efficiency improvement, 225 µW IC consumption, and 12 mW external power—over three times lower than regulatory limits.

Abstract

<?Pub Dtl=""?> Emerging applications in brain–machine interface systems require high-resolution, chronic multisite cortical recordings, which cannot be obtained with existing technologies due to high power consumption, high invasiveness, or inability to transmit data wirelessly. In this paper, we describe a microsystem based on electrocorticography (ECoG) that overcomes these difficulties, enabling chronic recording and wireless transmission of neural signals from the surface of the cerebral cortex. The device is comprised of a highly flexible, high-density, polymer-based 64-channel electrode array and a flexible antenna, bonded to 2.4 mm × 2.4 mm CMOS integrated circuit (IC) that performs 64-channel acquisition, wireless power and data transmission. The IC digitizes the signal from each electrode at 1 kS/s with 1.2 μV input referred noise, and transmits the serialized data using a 1 Mb/s backscattering modulator. A dual-mode power-receiving rectifier reduces data-dependent supply ripple, enabling the integration of small decoupling capacitors on chip and eliminating the need for external components. Design techniques in the wireless and baseband circuits result in over 16× reduction in die area with a simultaneous 3× improvement in power efficiency over the state of the art. The IC consumes 225 μW and can be powered by an external reader transmitting 12 mW at 300 MHz, which is over 3× lower than IEEE and FCC regulations.