A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design

Abstract

This paper explains modeling and analysis of RC-dominant wires for high-speed wireline transceiver design. A closed form formula derived from telegrapher’s equation accurately describes a frequency response of an RC-dominant wire, yet it is simple and intuitive for designers to easily understand design trade-offs without a complex numerical equation solver. This paper explains how the model is derived and how it can help designers in example transceiver designs.