Journal of Applied Physics · 2000 · 10 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureDigital CommunicationMicroelectronicsDevice ScalingError Control CodingLow-noise Circuit DesignMemory DevicesMemory Hierarchy DesignMemory Subsystem DesignAreal Density EffectsAreal Density LimitsSignal-to-noise RatioSignal-to-noise Ratio Analysis
Design considerations for areal densities beyond 20 Gb/in.2 are discussed, and in particular a demonstration at 24.8 Gb/in.2 is shown. The demonstrations used a single combined write and read head (Merge, Notched head). In this article we will discuss the tradeoffs in kilobytes per inch (KBPI) and tracks-per-inch in obtaining areal densities at 25 Gb/in.2 densities. The KBPI is limited by both the total signal-to-noise ratio and the nonlinear-transition shift. Simple estimates of the increase in channel performance from class IV partial response (PR4), extended partial response 4 (EPR4), and modified EEPR4, as well as the addition of codes which eliminate bit shift and tribit errors are discussed as large contributors to the increase in the areal density.
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