An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances

Abstract

We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.