A Low Power Inductorless LNA With Double ${\rm G} _{\rm m}$ Enhancement in 130 nm CMOS

Abstract

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> is -12 dBm for an input compression point of -21 dBm.