Investigation of candidate VRM topologies for future microprocessors [voltage regulator modules]

Abstract

Future generation microprocessors are expected to exhibit much heavier loads and much faster transient slew rates. Today's voltage regulator module (VRM) will need a large amount of extra decoupling and output filter capacitors to meet future requirements, which basically makes the existing VRM topologies impractical. In this paper, a candidate topology, interleaved quasi-square wave, is proposed. Its design, simulation and experimental results are presented.