Linearization of CMOS LNA's via optimum gate biasing

Abstract

A FET linearization technique based on optimum gate biasing is investigated at RF. A novel bias circuit is proposed to generate the gate voltage for zero 3rd-order nonlinearity of the FET transconductance. The measured data show that a peak in IIP/sub 3/ occurs at a gate voltage slightly different from the one predicted by the dc theory. The origins of this offset are explained based on a Volterra series analysis and confirmed experimentally. The technique was used in a 0.25 /spl mu/m CMOS cellular-band CDMA LNA. At the optimum bias, the amplifier achieved a NF of 1.8 dB, an IIP/sub 3/ of +10.5 dBm, and a power gain of 14.6 dB with a current consumption of only 2 mA from 2.7 V supply.