Design techniques of CMOS SCL circuits for Gb/s applications

Abstract

This paper presents the design techniques of Gb/s CMOS SCL circuits. Basic SCL functional cells including a 2:1 multiplexer, a D-latch, and XOR/NXOR, AND/NAND, OR/NOR gates are described in detail. Simulations show that a SCL static frequency divider can operate faster than a CMOS static logic one. Experimental results of an SCL 1:4 static frequency divider and an SCL 4:1 multiplexer both in 0.35 /spl mu/m CMOS technology prove that SCL circuits can be used in Gb/s applications.