A genetic approach to automatic bias generation for biased random instruction generation

Abstract

Biased random instruction generators are commonly used in architectural verification of microprocessors, with biases specified manually by designers. As the complexity of processors grows, so does the complexity of specifying biases. Automatic bias generation speeds up the verification flow and may lead to better coverage of potential design errors. In this work, we present a genetic algorithm based framework to automatically generate biases. We target utilization of specific buffers for a new version of the PowerPC architecture. Our results show that the GA is effective in achieving high buffer utilization. Also, in targeting multiple objectives, the best approach to use depends on whether the objectives are related.