2015 · 10 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignDynamic Power ReductionInterconnect DesignLeakage Power ReductionPower ManagementVoltage ScalingBoostingCapacitanceCapacitance ReductionCapacitive CouplingLow-voltage Cmos DesignSupply Voltage OptimizationUltra-low-voltage Circuit DesignVoltage
This paper presents new dynamic supply and interconnect boosting techniques for low voltage SRAMs and logic in deep 14nm FinFET technologies. The capacitive coupling in a FinFET device is used to dynamically boost the virtual logic and array supply voltage, improving V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> . Hardware measurements show a 2.5-3x access time improvement at lower voltages and a functional V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> down to 0.3V. Results are supported by novel physics-based capacitance extraction and novel superfast statistical circuit simulations.