A novel highly linear CMOS buffer

Abstract

A high input impedance, low output impedance, highly linear CMOS buffer is very desirable in many analog CMOS circuits. Conventional buffers employ feedback which severely limits bandwidth and linearity at even medium range frequencies. A recent open loop buffer, although linear, suffers from large power supply voltage requirement. This makes it undesirable for low voltage deep submicron processes. Here going to basics leads us to a very simple and very linear buffer which shows more than 26 dB THD improvement over conventional designs.