Back Enhanced (BE) SOI pMOSFET

Abstract

We report for the first time the fabrication of Back Enhanced (BE) SOI pMOSFET. In this device, there is no doping step process like ion implantation, diffusion or other kind of doping for formation of source/drain or channel, and it is a planar device. The source/drain is enhanced (holes accumulated at back interface) by applying a high negative voltage at back gate (substrate). The front gate voltage should be enough to pinch off the channel. This device is very simple to fabricate, and thus allows many universities an opportunity to fabricate your own device for educational purposes. Moreover, this device has also interesting features like a threshold voltage modulate by back gate from negative to positive (resulting in enhanced and depletion mode operation), a subthreshold slope of 77mV/dec, body factor of 1.11 and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> . The BE SOI MOSFET parameter is compatible with other devices with the same operation principle, i.e. current flows near to back interface, but it is much easier to fabricate, using only tree photolithography steps.