Publication | Closed Access
An integrated approach to pin assignment and global routing for VLSI building-block layout
11
Citations
8
References
2002
Year
Unknown Venue
Vlsi Building-block LayoutPhysical Design (Electronics)Global RoutingIntegrated ApproachVlsi DesignEngineeringElectronic Design AutomationVlsi ArchitectureArchitectural EngineeringRouter ArchitecturePin AssignmentComputer EngineeringComputer ArchitectureTotal Wire LengthNetwork On ChipInterconnection Network Architecture
An efficient algorithm integrating global routing, pin assignment, block reshaping and positioning, which is based on a rip-up and reroute and the simulated evolution technique, is presented. Experimental results show that the proposed algorithm achieves up to 10.5% reduction of chip area and up to 34.6% reduction of total wire length compared with previous methods.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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