Publication | Closed Access
Design of SEU-hardened CMOS memory cells: the HIT cell
65
Citations
6
References
2002
Year
Unknown Venue
Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringEmerging Memory TechnologyElectronic MemoryComputer EngineeringComputer ArchitectureMemory CellMemory DevicesSemiconductor MemoryElectrical PerformancesMicroelectronicsMemory ArchitectureHit Cell
A memory cell, called HIT cell (heavy ion tolerant cell), designed to be SEU-immune is presented. Compared to previously reported design hardened solutions, the HIT cell is less SEU-sensitive, features better electrical performances and consumes less silicon area.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
| Year | Citations | |
|---|---|---|
Page 1
Page 1