A 600 MSPS 8-bit folding ADC in 0.18 μm CMOS

Abstract

An 8-bit folding A/D converter (ADC) achieves signal-to-noise plus distortion ratio (SNDR) of 40 dB at 600 MSample/s (MSPS) for input signals up to 200 MHz in standard 0.18-/spl mu/m CMOS. Distributed T/Hs at outputs of the first-stage pre-amplifiers are employed instead of a dedicated front-end T/H. Lateral capacitors are inserted between adjacent T/H outputs to average the random mismatches in charge injection and clock skew among the distributed T/Hs. The ADC consumes 0.5-mm/sup 2/ effective chip area and dissipates 207mW from a 1.8V supply.