A novel architecture for efficient protocol processing in high speed communication environments

Abstract

The architecture, system modules and functional design of a reconfigurable protocol processor are presented. The protocol processor aims in accelerating execution of telecom transport protocols by extending a high-performance RISC core with reconfigurable pipelined hardware. CPU demanding and (hard) real-time protocol functions will be handled by the programmable hardware, while the remaining functions as well as higher layer protocols will be handled by the on-chip RISC in an integrated way. Applications that may take advantage of the protocol processor are also presented. Furthermore, the codesign techniques, followed for the implementation of the component, are analysed.