Minimizing Power Dissipation in Scan Circuits During Test Application

Abstract

Motivation for reducing power dissipation during test application is presented. A scheme for reducing power dissipation during test application, when scan test structure is used, is proposed. Algorithms required to exploit the proposed technique are discussed. Experimental results are presented. keywords: Power dissipation, Full Isolated Scan, Full Integrated Scan. 1. Introduction Growing size of VLSI circuits, along with the high transistor density, is making minimization of power dissipation an important issue in VLSI design. Power dissipation issues are addressed at various stages of circuit design. For example, circuits are synthesized so that average switching activity is reduced [1, 2, 3], technology mapping can be targeted for low power dissipation [4, 5], and physical design can be targeted for low power dissipation [6]. Power dissipation issues during test application must also be addressed. The motivation for this is discussed in section 2. Except for [7], we are unaware o...