Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations

Abstract

Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is the same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.