PMOS drain breakdown voltage walk-in: a new failure mode in high power BiCMOS applications

Abstract

High voltage power management applications often require 50V to 100V operation. These circuits are implemented in a BiCMOS processes and support both low voltage (5-15V) and high voltage devices. In these applications the high voltage PMOS (HV-PMOS) must operate at high currents, voltages (e.g. 80V) and temperatures (150/spl deg/C) while sustaining a drain breakdown voltage in excess of the device operating voltage. This paper examines an HV-PMOS failure mode identified during device qualification and high temperature operational life. This paper presents data on a new PMOS failure mechanism termed "drain breakdown voltage walk-in" not yet discussed in the literature.