CMOS VLSI Lukasiewicz logic arrays

Abstract

Lukasiewicz logic arrays (LLAs) are massively parallel analog computers organized as binary trees of identical processing elements. The authors have designed and performed preliminary tests on a series of CMOS VLSI LLAs whose cells perform Lukasiewicz implication ( to ). The authors describe the LLA architecture and its relationship to cellular automata, describe the CMOS VLSI implementation of versions LL9 and LL10 and their initial characterization, and report on the results obtained by programming LL9 and LL10 as fuzzy function recognizers, the first step in designing more general function units such as expert systems and neural networks. Initial test results showed that the LLAs implemented the notch function linearly, but with a slope that varied from that of the ideal function. Trimming the LLA inputs and outputs is expected to result in a typical error of less than 2%, and a mean error of less than 0.5%.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>