A 240 GHz Fully Integrated Wideband QPSK Receiver in 65 nm CMOS

Abstract

Operation at millimeter-wave/sub-terahertz frequencies allows one to realize very high data-rate transceivers for wireless chip-to-chip communication. In this paper, a 240 GHz 16 Gbps QPSK receiver is demonstrated in 65 nm CMOS technology. The receiver employs a direct-conversion mixer-first architecture with an integrated slotted loop antenna. A 240 GHz LO chain drives the passive mixers to down-convert the modulated data to baseband. The baseband signal is then amplified using high gain, wide bandwidth amplifiers. The receiver has a noise figure of 15 dB with a conversion gain of 25 dB calculated from measurement data. The receiver achieves a data rate of 10 Gbps (with ) and a maximum data rate of 16 Gbps (with BER of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> ) with a receiver efficiency of 16 pJ/bit.