Microarchitectural techniques to enable efficient java execution

Abstract

The Java Virtual Machine (JVM) is the corner stone of Java technology, and its efficiency in executing Java bytecodes is crucial for the success of this technology. Interpretation, Just-In-Time (JIT) compilation, and dedicated hardware realization are well known solutions for a JVM, and previous research has proposed optimizations for each of these techniques. This dissertation consists of comprehensive research on Java runtime systems, examining architectural issues from both hardware and JVM implementation perspectives to enable efficient Java runtime system development on a wide range of platforms and execution environments. Our research shows that software translation of Java bytecodes using interpreters and JIT compilers is the biggest bottleneck in Java performance. The actual operations required for producing the program results is only a small subset of the operations that happen during Java program execution using software translation. Software emulation is easy to implement for new platforms but cannot offer a solution for fast execution of Java bytecodes. Using hardware support to translate the bytecodes eliminates the requirement of a software layer to emulate the bytecodes. This dissertation proposes the use of a hardware acceleration unit that works in conjunction with a standard microprocessor to improve the execution performance of Java programs. The proposed Hard-Int architecture performs the translation of Java bytecodes to native code using hardware, thus eliminating much of the overhead of software translation. Performing hardware translation in a general purpose processor is seen to improve Java execution by upto 770% over an interpreter and upto 500% over a JIT compiler. This dissertation also investigates techniques to improve performance in a dedicated Java processor. Java processors which are typically stack machines, are limited by dependencies to the stack making it difficult to achieve high-performance due to limited instruction level paralellism. To address this problem we investigate cost-effective microarchitectural techniques to exploit parallelism in stack-based embedded Java processors.