Considerations on package design for high speed and high pin count CMOS devices

Abstract

High-speed, high-density CMOS VLSI devices have powerful output buffers to charge a load capacitance quickly, which causes large switching noise on the power/ground lines. Furthermore, the equivalent impedance of the output buffer becomes lower than the characteristic impedance of the transmission line on a board, which induces complicated phenomena, including ringing noise. These problems are discussed, and the electrical characteristics of a 348-pin QFP (quad flat package) developed for a 1-micron, 129-K gate CMOS gate array is described. The factors that determine switching noise were investigated by simulation that represents the packaging noise was designed and used to characterize the 348-pin QFP. Disagreement between measured data and simulation results remains to be investigated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>