Electrical characterization and modeling of simultaneous switching noise for leadframe packages

Abstract

Quad-flat packages with a leadframe made of copper (Cu), or alloy 42 are widely used for CMOS digital applications. As the clock speed of CMOS VLSIs increases, the package inductance is considered to be a limiting factor for their performance. To investigate the relationship between package inductance and switching noise, three types of leadframe materials, Cu, alloy 42, and Ag-plated alloy 42 were prepared. Frequency-dependent properties of leadframe materials were measured up to a high frequency range. Then, extensive experiments were executed by using a CMOS noise generating chip to measure how leadframe materials influence switching noise in conjunction with output buffer characteristics. The alloy 42 leadframe is believed to be unsuitable for high-speed CMOS applications because of its high permeability of ferromagnetics. However, it has been proved that the large inductance difference at lower frequencies does not greatly affect switching noise at practical operating frequencies. A modeling approach for leadframe packages was executed by taking mutual inductances into consideration and by using the measured values of inductances and resistance.