VINCI: VLSI implementation of the new secret-key block cipher IDEA

Abstract

A VLSI implementation of a novel secret-key block cipher is presented. Security considerations lead to novel system concepts in chip design including protection of sensitive information and failure detection capabilities. The VLSI chip implements data encryption and decryption in a single hardware unit. All important standardized modes of operation of block ciphers are supported. In addition, new modes are proposed and implemented to fully exploit the algorithm's inherent parallelism. With a system clock frequency of 25 MHz, this device permits a data conversion rate of more than 177 Mbit/s. The chip is the first silicon block encryption device that can be applied to on-line encryption in high-speed networking protocols like ATM (Asynchronous Transfer Mode) or FDDI (Fiber Distributed Data Interface). The high data throughput of 177.8 Mbit/s has been achieved by utilization of a sophisticated pipelining scheme and four full-custom modulo (2/sup 16/ + 1) multipliers. Two unidirectional high-speed 16-bit data ports guarantee continuous occupancy of the encryption unit.