1986 · 12 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignLow-power Digital Circuit DesignPhysical DesignPower ManagementCmos Digital Circuit DesignCmos ScalingDynamic Power DissipationLow-power Cmos DesignLow-voltage Cmos DesignMemory Circuit DesignUltra-low-power Cmos
This paper will cover a 32K×8 full CMOS SRAM with a divided word line that has been fabricated in single-poly, double-metal, P-well CMOS, Address access time is 30ns. Standby power dissipation is 500mW. The CMO5 memory cell using 6 transistors, designed in 1.0μm layout rules, measures 10.6μm <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">× 13.2μ</tex> m.
3
A 64Kb full CMOS RAM with divided word line structure
Masahiko Yoshimoto, Keiko Anami, Hirofumi Shinohara et al. · 1983 · 46 citations
Engineering, Computer Engineering, Electrical Engineering +14
A 256K CMOS SRAM with variable-impedance loads
S. Yamamoto, K. Uchibori, Kensaku Nagasawa et al. · 1985 · 17 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 4.5ns 256K CMOS SRAM with tri-level word line
Hirofumi Shinohara, Keiko Anami, K. Ichinose et al. · 1985 · 11 citations
Engineering, Computer Engineering, Electrical Engineering +10