Time domain current waveform simulation of CMOS circuits

Abstract

A time-domain current waveform simulator for the power buses of CMOS circuits is presented. The use of the simulated waveform helps solve VLSI reliability problems due to electromigration and excessive voltage drops in the power bus. Based on the event-driven technique and the precharacterized switch-level delay model, the simulator can handle circuits as large as 10/sup 3/ approximately 10/sup 4/ transistors in 10 approximately 100 CPU seconds on the Sun-3 workstation. The simulated waveform in worst cases may deviate only 20% from those computed by SPICE.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>