A processor for graph search algorithms

Abstract

This report will describe a programmable signal processor with a pipelined arithemetic unit capable of 40 MIPs operation in graph search kernel operations. Thus a fivefold improvement in speech and image processing algorithms can be obtained over conventional architectures The chip was fabricated in a 1.5μm CMOS technology, occupies 43.4mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and operates at 20MHz.