Journal of Applied Physics · 2000 · 20 citations · 11 references
EngineeringMaterials EngineeringMaterials ScienceNanotechnologySemiconductor DevicesSemiconductor MaterialsAmorphous MaterialsAmorphous SemiconductorsAmorphous SolidsChemical Vapor DepositionNanoelectronicsSemiconductor NanomaterialsAmorphous SiliconCoulomb BlockadeLow-pressure Chemical Vapor DepositionNanocrystal SynthesisNanocrystalsOxidationSelective OxidationThreshold Voltage
The process to make nanocrystals with an average size <5 nm and a spatial density >1012/cm2 was proposed using agglomeration and partial oxidation of thin amorphous Si0.7Ge0.3 layer deposited in between the SiO2 layers by low pressure chemical vapor deposition. The reason to use an amorphous layer is to make it possible to deposit a thin continuous layer with a thickness of less than 5 nm. Si0.7Ge0.3 alloy layer was used to control the spatial density of the nanocrystals by using selective oxidation of Si in Si0.7Ge0.3 alloy layer. The single electron memory, similar to a flash type memory device was fabricated using these Si0.7Ge0.3 nanocrystals. The Coulomb blockade effect could be clearly observed at room temperature with a threshold voltage shift of about 2.4 V, which demonstrated the formation of nanocrystals with a high spatial density.
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A silicon nanocrystals based memory
Sandip Tiwari, Farhan Rana, Hussein Hanafi et al. · Applied Physics Letters · 1996 · 1.6K citations
Room-temperature single-electron memory
Kazuo Yano, T. Ishii, T. Hashimoto et al. · IEEE Transactions on Electron Devices · 1994 · 434 citations
Engineering, Computer Engineering, Electrical Engineering +15
Kazuhiko Nakazato, Richard J. Blaikie, H. Ahmed · Journal of Applied Physics · 1994 · 149 citations
Engineering, Computer Engineering, Electrical Engineering +9