Implementation of MCML universal logic gate for 10 GHz-range in 0.13 μm CMOS technology

Abstract

In this work/sup 1/ an optimization method for designing the universal MOS Current Mode Logic (MCML) gate for high-speed applications is developed. The optimization method is then applied to the standard and two modified topologies of the universal logic gate that are proposed in this article. The target frequency of operation is 10 GHz and above. The reported results are compared in terms of speed, area, and power dissipation. The modified topologies improve the speed by 25% to 30% over that of the standard topology, while dissipating the same amount of power. All simulations are done in a 0.13 /spl mu/m standard CMOS process, using Spectre simulator.