Publication | Closed Access
A CMOS 160 Mb/s phase modulation I/O interface circuit
15
Citations
2
References
2002
Year
Unknown Venue
EngineeringComputer ArchitectureInterconnection Network ArchitectureHardware SystemsElectromagnetic CompatibilityHigh RatesClock RecoveryMhz ClockMixed-signal Integrated CircuitSystems EngineeringUltra-low LatencyElectrical EngineeringComputer EngineeringNetwork On ChipHigh-speed NetworkingExtra Wide BusesMicroelectronicsNetwork TimingCmos 160
This paper proposes an approach to data transfer that can potentially achieve high rates without requiring the ultra fast clocks of other approaches, or extra wide buses. The idea is to transfer multiple bits over each pin within each clock cycle using modulation techniques common in communication systems. Phase modulation is simple in implementation and demonstrates 160 Mb/s peak transfer rate per pin using a 20 MHz clock. This scheme may prove effective for chip-to-chip or system bus interface both on printed circuit boards (PCBs) and multi-chip modules (MCMs).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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