A 6 b 1.1 GSample/s CMOS A/D converter

Abstract

High-speed ADCs are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6 b while the sampling rate (Fs) and effective resolution bandwidth (ERBW) requirements increase with each generation of storage system. Sample rates up to 800 MSample/s have been reported with ERBW=200 MHz. The ADC presented here achieves a maximum sample rate of 1.1 GSample/s and an EBBW of 450 MHz. This result is obtained with full flash interpolating/averaging architecture with distributed track-and-hold (T/H) in a standard 0.35 μm single-poly five-metal 3.3 V digital CMOS process. Chip area is 0.35 mm/sup 2/ and power consumption is 300 mW.