Hardware Implementation of a Lossless Image Compression Algorithm Using a Field Programmable Gate Array

Abstract

We describe a hardware implementation of a state-of-the-art lossless image compression algorithm. The algorithm is based on the LOCO-I (low complexity lossless compression for images) algorithm developed by Weinberger, Seroussi, and Sapiro, with modiflcations to lower the implementation complexity. In this setup, the compression itself is performed entirely in hardware using a fleld programmable gate array and a small amount of random access memory. The compression speed achieved is 1.33 Mpixels/second. Our algorithm yields about 15 percent better compression than the Rice algorithm.