2002 · 14 citations · 2 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMicroelectronicsSystem-on-chip DesignInstruction Set ArchitectureInterconnect ArchitectureMicroarchitecture DesignMulticore Processor DesignProcessor Core DesignProcessor MicroarchitectureAccelerator MicroarchitectureData Cache BehaviorInterconnect OptimizationLow-power MicroarchitectureMulticore Processor ArchitectureSystem-on-chip HierarchySystem-on-chip IntegrationVliw Microarchitecture
The MAJC 5200 is a dual 32b microprocessor system-on-a-chip, utilizing 0.22 /spl mu/m CMOS with all-Cu interconnect. Two CPUs, delivering GGFLOPS and 13GOPS at 500 MHz, are tightly coupled through a shared, coherent, 4-way set associative 16 KB data cache, and an on-chip 4 GB/s switch. Each CPU is a 4-issue VLIW engine.
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The MAJC architecture: a synthesis of parallelism and scalability
Shing Sheung Tse, A.W. Conigliam, Shailender Chaudhry et al. · IEEE Micro · 2000 · 93 citations
Implementation of a 3rd-generation SPARC V9 64 b microprocessor
R. Heald, K. Aingaran, C. Amir et al. · 2002 · 37 citations