2003 · 37 citations · 0 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysHardware Description LanguagesField-programmable Gate Array ArchitectureLogic SynthesisMemory Subsystem DesignMicroarchitecture DesignRegister AllocationRegister-transfer Level DesignCounter DesignHardware GenerationHardware GeneratorsHardware SynthesisMemory MappingRegister-transfer Level GenerationRegister-transfer Level Hardware ModelingRegister-transfer Level Synthesis
An approach is described for addressing generation hardware synthesis. The authors present algorithms and tools that describe the hardware between a binary counter and the address port of a block of memory, which is accessed in some repetitive pattern. These tools match results produced manually for examples taken from a VLSI image processing application.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>