Publication | Closed Access
Synthesis of address generators
35
Citations
0
References
2003
Year
Unknown Venue
Hardware SecurityEngineeringHardware EmulationAddress PortFormal MethodsComputer ArchitectureComputer EngineeringHardware Description LanguageBinary CounterSystem SynthesisComputer ScienceProcessor ArchitectureSequence DesignHardware SystemsGeneration Hardware SynthesisPseudorandom Number GeneratorHardware ArchitectureAddress Generators
An approach is described for addressing generation hardware synthesis. The authors present algorithms and tools that describe the hardware between a binary counter and the address port of a block of memory, which is accessed in some repetitive pattern. These tools match results produced manually for examples taken from a VLSI image processing application.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>