A 10Gb/s CDR with a half-rate bang-bang phase detector

Abstract

A 10Gb/s PLL-based Clock and Data Recovery (CDR) circuit, with a half-rate bang-bang phase detector, is implemented using a 0.13/spl mu/m CMOS technology. The clock frequency is 5GHz, generated using a fully differential four-stage VCO. The loop filter is implemented on chip. The design meets the requirements of the local area network (LAN). applications. The total power dissipation of the CDR is less than 150mW.