A mixed QoS SDRAM controller for FPGA-based high-end image processing

Abstract

High-end video and multimedia processing applications today require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, accessing SDRAM is a complex task, especially if multi-stream access, different stream types and realtime capability are an issue. The paper describes a multi-stream SDRAM controller IP (intellectual property) that covers different stream types and applies memory scheduling to achieve high bandwidth utilization. Two different architectures are presented and discussed; simulation results with a realistic application configuration demonstrate up to 90% of maximum memory bandwidth utilization. The scheduler IP is suitable for FPGA implementation and is flexible enough to be used in other applications.