Low power CMOS dynamic latch comparators

Abstract

The paper proposes three new low power CMOS dynamic latch comparators suitable for pipeline analog-to-digital converters. All three use the same differential comparing circuit that can be modeled as variable resistors to trigger the switching behavior of a cross coupled latch. However, their dynamic behaviors during the reset phase are different. The first one precharges the two outputs at HIGH state. The second one discharges the outputs at slightly above the threshold voltage. The third one uses charge sharing to attain approximately half the supply voltage at both outputs. Preliminary simulation shows that the charge sharing technique yields lowest power consumption of 90 /spl mu/W at 100 MHz. All three comparators have an offset voltage in the range of 30-150 mV.