An asynchronous low-power 80C51 microcontroller

TLDR

The paper presents a low‑power asynchronous implementation of the 80C51 microcontroller. The design is a compiled VLSI program written in Tangram and automatically compiled to a standard‑cell netlist. The implementation achieves a four‑fold power reduction versus a recent synchronous design, remains fully bit‑compatible, and supports timing‑compatible external memory access while enabling exploration of design alternatives.

Abstract

This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 /spl mu/ CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool-set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.