Parallel FPGA Implementation of RSA with Residue Number Systems—Can side-channel threats be avoided?

Abstract

In this paper, the authors presented a new parallel architecture to avoid side-channel analysis such as: timing attack, simple/differential power analysis, fault induction attack and simple/differential electromagnetic analysis. Montgomery multiplication based on residue number systems was used. Thanks to RNS, a design which is able to perform an RSA signature in parallel on was developed a set of identical and independent coprocessors. Of independent interest, the authors proposed a new DPA countermeasure when RNS are used that is only (slightly) memory consuming. Finally, the new architecture was synthesized on FPGA and it presents promising performance results. Even if the aim is to sketch a secure architecture, the RSA signature is performed in less than 150 ms, with competitive hardware resources. To the authors' knowledge, this is the first proposal of an architecture counteracting electromagnetic analysis apart from hardware countermeasures reducing electromagnetic radiations